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Job number JO-200528-218627

Company overview

Our client is a world-leading semiconductor company.

Job description

The IC Layout Engineer (Physical Designer) is responsible for the development and preparation of multi-dimensional layouts (physical design) and detailed drawings of the semiconductor devices from schematics and related geometry provided by the design engineering team to be implemented through the use of CAD tools. He/She will be responsible for the checking and verification of the completed physical design and will also be part of the initiatives that will help with the development of the layout team.

This role may also be involved in mentoring layout trainees.

Requirements

-Graduate of BS Electronics or Electrical Engineering
-At least 5 years of experience in full custom analog layout (physical design)
-Experience on Linux, Cadence Virtuoso XL (6.17 or 6.18) and Calibre Physical Layout Verification tools
-Extensive process knowledge on 0.18um CMOS/BCD, 40nm, 28nm, 16nm or lower geometries
-Analog layout experience on any of the following areas: Precision Converters/Amplifiers, RFICs, PMICs, and Integrated Platforms
-Experience on floor planning, top-level and section-level analog layout
-Knowledgeable on electro-migration, latch-up, antenna effect, crosstalk, matching, power routing, parasitics and isolation techniques
-Knowledgeable on LDE
-Knowledgeable in Cadence skill programming is an advantage

Contact Loraine Aguilar

Loraine Aguilar

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